Bio:

C.K. Cheng received early degrees from National Taiwan University, and his Ph.D. in electrical engineering and computer science from U.C. Berkeley in 1984. From 1984-86, he was a senior CAD engineer at Advanced Micro Devices, before joining the UCSD faculty in 1986. In 1991, Cheng won the School of Engineering's NCR Best Teaching Award. In 1999, he served as chief scientist at Mentor Graphics. Cheng was named an IEEE Fellow in 2000, and has won multiple awards, most recently, the CAD Transactions Best Paper Award for 2002 from the IEEE Circuits and Systems Society. Since 1994, Cheng has been associate editor of IEEE Transactions on CAD, and he has participated on numerous conference committees, including the June 2000 ACM/IEEE Design Automation Conference. Cheng has consulted for a number of system, design, and electronic design automation companies.

Professor Cheng's research interests include network optimization and design automation on microelectronic circuits. He works in the area of circuit design of systems-on-chip that require integration of systems in ever-smaller dimensions. Cheng focuses on circuit analysis and floorplanning (the layout of the chip), including field programmable components, interconnect architectures, and adaptive data path modules. For circuit analysis, Cheng develops efficient methods to model and check the signal integrity of huge networks. This includes establishing circuit design guidelines that minimize crosstalk and power-supply fluctuations, while at the same time balancing delay and the amount of ringing. Floorplan optimization is considered to be one pivotal step in the deep submicron design methodology. Cheng's research on this topic aims to provide very high return toward achieving parity between technology capability and design productivity. His research team studies interconnect architecture, performance-driven layout planning, and adaptive data path modules, which constitute critical ingredients of system on chip designs.